Testing can occur in three different phases of a system on a chip (SoC) life-cycle: a manufacturing test (MFGT), a power-on-self-test (POST), and a mission mode self-test (MMST). Each phase of the testing process carries its own requirements and goals.
In the first phase of testing, MFGT, memories are tested with a memory built-in self-test (MBIST) using a set of data backgrounds and algorithms. In particular, the MBIST first writes information into the memory cell arrays and then reads output information from the memory cell arrays for comparison against expected data. An exhaustive set of built-in and programmable tests are usually run during MFGT. The purpose of these tests is to try to remove bad chips from the pool which will eventually be packaged into products, thereby improving the initial quality of the shipped product. Further, these tests are destructive, i.e., the original memory data content is not preserved.
The second phase of testing, POST, varies dependent on the technology node and market that the SoC is targeting. As its name implies, POST occurs when the SoC is activated prior to normal operations commencing, e.g., once the power-on button of a device is activated. POST goals vary from MFGT. For example, test time limitations become more prominent compared to MFGT, especially in battery operated, hand-held devices as users have functional device availability expectations once the power-on button is engaged. As such, the quality level of testing for POST is not as stringent as MFGT because it is assumed that the SoC had been thoroughly tested at MFGT. In other words, POST is more of a sign-off test, e.g., go/no-go indication, prior to customer use. Specifically, POST ensures that the SoC will operate as expected during functional operation until the next POST (e.g., the next time the power-on button is activated). However, similar to MFGT, the tests during POST are also destructive, i.e., the original memory data content is not preserved.
The third phase of testing, MMST, is performed during operational periods between POST operations. During MMST, logical partitions within the chip are designed to be temporarily varied offline during normal functional operations, enabling some level of testing, e.g., MBIST, to occur on that partition while the rest of the device is functionally operational. However, as noted above, MBIST is generally destructive and, therefore, the data within the tested partition must first be saved and then restored as the partition varies offline and then back online. Further, the real time operating system (“RTOS”) of the SoC allocates a time slice during which the saving of the partition's data, testing of the partition's memories, and restoring of the partition's data must all be handled. In other words, test time is critical during MMST. As such, any time spent saving and restoring the partition's data will be seen as overhead. In addition, saving and restoring the partition's data also requires additional chip area resources resulting in still more overhead.
Accordingly, there is a need to efficiently test memories during MMST without destroying any functional data within the tested memories.